Low-density parity-check (LDPC) codes are a class of error-correcting codes that may be efficiently encoded and decoded in hardware. LDPC codes are linear codes that have sparse parity-check matrices. The sparseness of the parity-check matrices allows for relatively fast decoding and computationally-inexpensive error correction. Many practical LDPC code designs use quasi-cyclic (QC) LDPC codes to yield more efficient hardware parallelization. Layered decoding is an efficient way of decoding LDPC codes and is commonly used in a wide range of applications. More specifically, layered decoding offers multiple opportunities for parallel implementation. For example, an LDPC decoder implementing layered decoding may be capable of processing multiple rows of a parity-check matrix in a single cycle. However, the number of cycles needed to process an entire layer of a base matrix associated with a QC LDPC code may depend on the hardware resources of the decoder. Accordingly, it may be desirable to optimize the number of parallel decoding operations that can be performed by an LDPC decoder, when decoding QC LDPC codes, based at least in part on the available resources of the decoder.